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雙極性晶體管

二極管

ESD保護(hù)、TVS、濾波和信號(hào)調(diào)節(jié)ESD保護(hù)

MOSFET

氮化鎵場(chǎng)效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應(yīng)用認(rèn)證產(chǎn)品(AEC-Q100/Q101)

74AUP1T97GM

Low-power configurable gate with voltage-level translator

The 74AUP1T97 is a configurable multiple function gate with level translating, Schmitt-trigger inputs. The device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. Low threshold Schmitt trigger inputs allow these devices to be driven by 1.8 V logic levels in 3.3 V applications. This device ensures very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 2.3 V to 3.6 V

  • CMOS low power dissipation

  • High noise immunity

  • Overvoltage tolerant inputs to 3.6 V

  • Low noise overshoot and undershoot < 10 % of VCC

  • IOFF circuitry provides partial power-down mode operation

  • Latch-up performance exceeds 100 mA per JESD 78 Class II

  • Low static power consumption; ICC = 1.5 μA (maximum)

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

參數(shù)類型

型號(hào) VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) fmax (MHz) Nr of bits Power dissipation considerations Tamb (°C) Rth(j-a) (K/W) Ψth(j-top) (K/W) Rth(j-c) (K/W) Package name
74AUP1T97GM 2.3?-?3.6 CMOS ± 4 3.9 70 1 ultra low -40~125 290 6.5 145 XSON6

PCB Symbol, Footprint and 3D Model

Model Name 描述

Register once, drag and drop ECAD models into your CAD tool and speed up your design.

Click here for more information

封裝

型號(hào) 可訂購的器件編號(hào),(訂購碼(12NC)) 狀態(tài) 標(biāo)示 封裝 外形圖 回流焊/波峰焊 包裝
74AUP1T97GM 74AUP1T97GM,115
(935280469115)
Active 59 SOT886
XSON6
(SOT886)
SOT886 REFLOW_BG-BD-1
SOT886_115
74AUP1T97GM,132
(935280469132)
Active 59 SOT886_132

環(huán)境信息

型號(hào) 可訂購的器件編號(hào) 化學(xué)成分 RoHS RHF指示符
74AUP1T97GM 74AUP1T97GM,115 74AUP1T97GM rohs rhf rhf
74AUP1T97GM 74AUP1T97GM,132 74AUP1T97GM rohs rhf rhf
品質(zhì)及可靠性免責(zé)聲明

文檔 (16)

文件名稱 標(biāo)題 類型 日期
74AUP1T97 Low-power configurable gate with voltage-level translator Data sheet 2023-07-17
AN10161 PicoGate Logic footprints Application note 2002-10-29
Nexperia_document_guide_Logic_translators Nexperia Logic Translators Brochure 2021-04-12
Nexperia_document_guide_MiniLogic_MicroPak_201808 MicroPak leadless logic portfolio guide Brochure 2018-09-03
SOT886 3D model for products with SOT886 package Design support 2019-10-03
aup1t97 aup1t97 IBIS model IBIS model 2015-09-06
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Leaflet 2019-04-12
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
DFN1410-6_SOT886_mk plastic, extremely thin small outline package; no leads; 6 terminals; 0.6 mm pitch; 1 mm x 1.45 mm x 0.5 mm body Marcom graphics 2017-01-28
XSON6_SOT886_mk plastic, extremely thin small outline package; no leads; 6 terminals; 0.6 mm pitch; 1 mm x 1.45 mm x 0.5 mm body Marcom graphics 2017-01-28
SOT886 plastic, leadless extremely thin small outline package; 6 terminals; 0.5 mm pitch; 1 mm x 1.45 mm x 0.5 mm body Package information 2022-06-01
SOT886_115 XSON6; Reel pack for SMD, 7''; Q1/T1 product orientation Packing information 2020-04-21
SOT886_132 XSON6; Reel pack for SMD, 7''; Q3/T4 product orientation Packing information 2020-04-21
74AUP1T97GM_Nexperia_Product_Reliability 74AUP1T97GM Nexperia Product Reliability Quality document 2024-06-16
REFLOW_BG-BD-1 Reflow soldering profile Reflow soldering 2021-04-06
MAR_SOT886 MAR_SOT886 Topmark Top marking 2013-06-03

支持

如果您需要設(shè)計(jì)/技術(shù)支持,請(qǐng)告知我們并填寫 應(yīng)答表 我們會(huì)盡快回復(fù)您。

模型

文件名稱 標(biāo)題 類型 日期
aup1t97 aup1t97 IBIS model IBIS model 2015-09-06
SOT886 3D model for products with SOT886 package Design support 2019-10-03

PCB Symbol, Footprint and 3D Model

Model Name 描述

Register once, drag and drop ECAD models into your CAD tool and speed up your design.

Click here for more information

訂購、定價(jià)與供貨

型號(hào) Orderable part number Ordering code (12NC) 狀態(tài) 包裝 Packing Quantity 在線購買
74AUP1T97GM 74AUP1T97GM,115 935280469115 Active SOT886_115 5,000 訂單產(chǎn)品
74AUP1T97GM 74AUP1T97GM,132 935280469132 Active SOT886_132 5,000 訂單產(chǎn)品

樣品

作為 Nexperia 的客戶,您可以通過我們的銷售機(jī)構(gòu)訂購樣品。

如果您沒有 Nexperia 的直接賬戶,我們的全球和地區(qū)分銷商網(wǎng)絡(luò)可為您提供 Nexperia 樣品支持。查看官方經(jīng)銷商列表。

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

可訂購部件

型號(hào) 可訂購的器件編號(hào) 訂購代碼(12NC) 封裝 從經(jīng)銷商處購買
74AUP1T97GM 74AUP1T97GM,115 935280469115 SOT886 訂單產(chǎn)品
74AUP1T97GM 74AUP1T97GM,132 935280469132 SOT886 訂單產(chǎn)品
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