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Click here for more information74AVC16836ADGG
20-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state
The 74AVC16836A is a 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP).
This product is designed to have an extremely fast propagation delay and a minimum amount of power consumption.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor (Live Insertion).
A Dynamic Controlled Output (DCO) circuitry is implemented to support termination line drive during transient.
Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-1A (2.7 V to 3.6 V)
CMOS low power consumption
Input/output tolerant up to 3.6 V
Dynamic Controlled Output (DCO) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation
Low inductance multiple VCC and GND pins to minimize noise and ground bounce
Power off disables 74AVC16836A outputs, permitting Live Insertion
Integrated input diodes to minimize input overshoot and undershoot
Applications
參數(shù)類型
| 型號(hào) | Package name |
|---|---|
| 74AVC16836ADGG | TSSOP56 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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封裝
下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。
| 型號(hào) | 可訂購(gòu)的器件編號(hào)，（訂購(gòu)碼(12NC)） | 狀態(tài) | 標(biāo)示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AVC16836ADGG | 74AVC16836ADGG,112 (935267933112) |
Obsolete | 74AVC16836ADGG |
TSSOP56 (SOT364-1) |
SOT364-1 |
SSOP-TSSOP-VSO-WAVE
|
暫無(wú)信息 |
| 74AVC16836ADGG,118 (935267933118) |
Obsolete | 74AVC16836ADGG | SOT364-1_118 |
環(huán)境信息
下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。
| 型號(hào) | 可訂購(gòu)的器件編號(hào) | 化學(xué)成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AVC16836ADGG | 74AVC16836ADGG,112 | 74AVC16836ADGG |
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| 74AVC16836ADGG | 74AVC16836ADGG,118 | 74AVC16836ADGG |
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Series
文檔 (10)
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| 74AVC16836A | 20-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state | Data sheet | 2018-09-24 |
| AN90007 | Pin FMEA for AVC family | Application note | 2018-11-30 |
| SOT364-1 | 3D model for products with SOT364-1 package | Design support | 2020-01-22 |
| av836a15 | av836a15 IBIS model | IBIS model | 2013-04-08 |
| av836a18 | av836a18 IBIS model | IBIS model | 2013-04-08 |
| av836a25 | av836a25 IBIS model | IBIS model | 2013-04-08 |
| av836a33 | av836a33 IBIS model | IBIS model | 2013-04-08 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| SOT364-1 | plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm body | Package information | 2022-06-23 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
Longevity
The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.
模型
| 文件名稱 | 標(biāo)題 | 類型 | 日期 |
|---|---|---|---|
| av836a15 | av836a15 IBIS model | IBIS model | 2013-04-08 |
| av836a18 | av836a18 IBIS model | IBIS model | 2013-04-08 |
| av836a25 | av836a25 IBIS model | IBIS model | 2013-04-08 |
| av836a33 | av836a33 IBIS model | IBIS model | 2013-04-08 |
| SOT364-1 | 3D model for products with SOT364-1 package | Design support | 2020-01-22 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
|
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74AVC16836ADGG
20-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state
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