可訂購部件
| 型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經(jīng)銷商處購買 |
|---|---|---|---|---|
| 74AVCH2T45DC | 74AVCH2T45DC,125 | 935283721125 | SOT765-1 | 訂單產(chǎn)品 |
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Click here for more information74AVCH2T45DC
Dual-bit, dual-supply voltage level translator/transceiver; 3?-?state
The 74AVCH2T45 is a dual bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.
The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are in the high-impedance OFF-state.
The 74AVCH2T45 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.
Alternatives
Features and benefits
Wide supply voltage range: 0.8 V to 3.6 V for VCC(A) and VCC(B)
High noise immunity
Suspend mode
Bus hold on data inputs
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Maximum data rates:
500 Mbps (1.8 V to 3.3 V translation)
320 Mbps (< 1.8 V to 3.3 V translation)
320 Mbps (translate to 2.5 V or 1.8 V)
280 Mbps (translate to 1.5 V)
240 Mbps (translate to 1.2 V)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3B exceeds 8000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
參數(shù)類型
| 型號 | VCC(A) (V) | VCC(B) (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | Category |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AVCH2T45DC | 0.8?-?3.6 | 0.8?-?3.6 | CMOS/LVTTL | ± 12 | 2.1 | 2 | very low | -40~125 | 205 | 35.3 | 115 | VSSOP8 | Bi-directional | Direction controlled |
PCB Symbol, Footprint and 3D Model
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封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AVCH2T45DC | 74AVCH2T45DC,125 (935283721125) |
Active | K45 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 |
Series
文檔 (12)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74AVCH2T45 | Dual-bit, dual-supply voltage level translator/transceiver; 3?-?state | Data sheet | 2024-08-12 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN90007 | Pin FMEA for AVC family | Application note | 2018-11-30 |
| Nexperia_document_guide_Logic_translators | Nexperia Logic Translators | Brochure | 2021-04-12 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
| avch2t45 | 74AVCH2T45 Ibis model | IBIS model | 2014-10-14 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| VSSOP8_SOT765-1_mk | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Marcom graphics | 2017-01-28 |
| SOT765-1 | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Package information | 2022-06-03 |
| SOT765-1_125 | VSSOP8; Reel pack for SMD, 7''; Q3/T4 product orientation | Packing information | 2020-04-21 |
| 74AVCH2T45DC_Nexperia_Product_Reliability | 74AVCH2T45DC Nexperia Product Reliability | Quality document | 2025-03-20 |
Longevity
The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.
PCB Symbol, Footprint and 3D Model
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訂購、定價與供貨
| 型號 | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74AVCH2T45DC | 74AVCH2T45DC,125 | 935283721125 | Active | SOT765-1_125 | 3,000 | 訂單產(chǎn)品 |
樣品
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74AVCH2T45DC
Dual-bit, dual-supply voltage level translator/transceiver; 3?-?state
從安世半導體購買
| SKU | 庫存* | MOQ | 單位價格 | 數(shù)量 |
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