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雙極性晶體管

二極管

ESD保護(hù)、TVS、濾波和信號調(diào)節(jié)ESD保護(hù)

MOSFET

氮化鎵場效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應(yīng)用認(rèn)證產(chǎn)品(AEC-Q100/Q101)

74CBTLV16211DGG

24-bit bus switch

The 74CBTLV16211 provides a dual 12-bit high-speed bus switch with separate output enable inputs (1OE, 2OE). The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The switch is disabled (high-impedance OFF-state) when the output enable (nOE) input is HIGH.

To ensure the high-impedance OFF-state during power-up or power-down, 1OE and 2OE should be tied to the VCC through a pull-up resistor. The minimum value of the resistor is determined by the current-sinking capability of the driver.

Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 2.3 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

此產(chǎn)品已停產(chǎn)

Features and benefits

  • Supply voltage range from 2.3 V to 3.6 V
  • High noise immunity
  • Complies with JEDEC standard:
    • JESD8-5 (2.3 V to 2.7 V)
    • JESD8-B/JESD36 (2.7 V to 3.6 V)
  • ESD protection:
    • HBM JESD22-A114F exceeds 2000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM AEC-Q100-011 revision B exceeds 1000 V
  • 5 Ω switch connection between two ports
  • Rail to rail switching on data I/O ports
  • CMOS low power consumption
  • Latch-up performance exceeds 250 mA per JESD78B Class I level A
  • IOFF circuitry provides partial Power-down mode operation
  • TSSOP56 packages: SOT364-1 and SOT481-2
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Applications

參數(shù)類型

型號 Package name
74CBTLV16211DGG TSSOP56

封裝

下表中的所有產(chǎn)品型號均已停產(chǎn) 。

型號 可訂購的器件編號,(訂購碼(12NC)) 狀態(tài) 標(biāo)示 封裝 外形圖 回流焊/波峰焊 包裝
74CBTLV16211DGG 74CBTLV16211DGG;11
(935284846112)
Obsolete CBTLV16211 Standard Procedure Standard Procedure SOT364-1
TSSOP56
(SOT364-1)
SOT364-1 SSOP-TSSOP-VSO-WAVE
暫無信息
74CBTLV16211DGG,11
(935284846118)
Obsolete CBTLV16211 Standard Procedure Standard Procedure SOT364-1_118

環(huán)境信息

下表中的所有產(chǎn)品型號均已停產(chǎn) 。

型號 可訂購的器件編號 化學(xué)成分 RoHS RHF指示符
74CBTLV16211DGG 74CBTLV16211DGG;11 74CBTLV16211DGG rohs rhf rhf
74CBTLV16211DGG 74CBTLV16211DGG,11 74CBTLV16211DGG rohs rhf rhf
品質(zhì)及可靠性免責(zé)聲明

文檔 (6)

文件名稱 標(biāo)題 類型 日期
74CBTLV16211 24-bit bus switch Data sheet 2016-11-09
SOT364-1 3D model for products with SOT364-1 package Design support 2020-01-22
cbtlv16211 74CBTLV16211 IBIS model IBIS model 2015-04-20
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT364-1 plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm body Package information 2022-06-23
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

如果您需要設(shè)計/技術(shù)支持,請告知我們并填寫 應(yīng)答表 我們會盡快回復(fù)您。

模型

文件名稱 標(biāo)題 類型 日期
cbtlv16211 74CBTLV16211 IBIS model IBIS model 2015-04-20
SOT364-1 3D model for products with SOT364-1 package Design support 2020-01-22

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

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