可訂購部件
| 型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經(jīng)銷商處購買 |
|---|---|---|---|---|
| 74LVC16240ADGG-Q100 | 74LVC16240ADGG-Q1J | 935302655118 | SOT362-1 | 訂單產(chǎn)品 |
Register once, drag and drop ECAD models into your CAD tool and speed up your design.
Click here for more information74LVC16240ADGG-Q100
16-bit buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
The 74LVC16240A-Q100 is a 16-bit inverting buffer/line driver with 3-state outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The device features four output enables (1OE, 2OE, 3OE and 4OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
MULTIBYTE flow-through standard pinout architecture
Low inductance multiple power and ground pins for minimum noise and ground bounce
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
參數(shù)類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC16240ADGG-Q100 | 1.2?-?3.6 | CMOS/LVTTL | ± 24 | 175 | 16 | low | -40~125 | 82 | 2 | 37 | TSSOP48 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
|
|
封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC16240ADGG-Q100 | 74LVC16240ADGG-Q1J (935302655118) |
Active | LVC16240A |
TSSOP48 (SOT362-1) |
SOT362-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT362-1_118 |
環(huán)境信息
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC16240ADGG-Q100 | 74LVC16240ADGG-Q1J | 74LVC16240ADGG-Q100 |
|
|
Series
文檔 (11)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC16240A_Q100 | 16-bit buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state | Data sheet | 2024-03-20 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| AN263 | Power considerations when using CMOS and BiCMOS logic devices | Application note | 2023-02-07 |
| SOT362-1 | 3D model for products with SOT362-1 package | Design support | 2020-01-22 |
| lvc16240a | lvc16240a IBIS model | IBIS model | 2013-04-08 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP48_SOT362-1_mk | plastic, thin shrink small outline package; 48 leads; 0.5 mm pitch; 12.8 mm x 6.1 mm x 1.2 mm body | Marcom graphics | 2017-01-28 |
| SOT362-1 | plastic thin shrink small outline package; 48 leads; body width 6.1 mm | Package information | 2024-01-05 |
| SOT362-1_118 | TSSOP48; Reel pack for SMD, 13''; Q1/T1 product orientation | Packing information | 2020-04-21 |
| 74LVC16240ADGG-Q100_Nexperia_Product_Reliability | 74LVC16240ADGG-Q100 Nexperia Product Reliability | Quality document | 2025-03-20 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
Longevity
The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
|
|
訂購、定價與供貨
| 型號 | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74LVC16240ADGG-Q100 | 74LVC16240ADGG-Q1J | 935302655118 | Active | SOT362-1_118 | 2,000 | 訂單產(chǎn)品 |
樣品
作為 Nexperia 的客戶，您可以通過我們的銷售機構(gòu)訂購樣品。
如果您沒有 Nexperia 的直接賬戶，我們的全球和地區(qū)分銷商網(wǎng)絡(luò)可為您提供 Nexperia 樣品支持。查看官方經(jīng)銷商列表。
How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74LVC16240ADGG-Q100
16-bit buffer/line driver with 5 V tolerant inputs/outputs; inverting; 3-state
從安世半導體購買
| SKU | 庫存* | MOQ | 單位價格 | 數(shù)量 |
|---|