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雙極性晶體管

二極管

ESD保護(hù)、TVS、濾波和信號(hào)調(diào)節(jié)ESD保護(hù)

MOSFET

氮化鎵場(chǎng)效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應(yīng)用認(rèn)證產(chǎn)品(AEC-Q100/Q101)

74LVC2G38GM

Dual 2-input NAND gate; open drain

The 74LVC2G38 is a dual 2-input NAND gate with open-drain outputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

此產(chǎn)品已停產(chǎn)

Features and benefits

  • Wide supply voltage range from 1.65 V to 5.5 V

  • 5 V tolerant outputs for interfacing with 5 V logic

  • Overvoltage tolerant inputs to 5.5 V

  • High noise immunity

  • CMOS low power dissipation

  • IOFF circuitry provides partial Power-down mode operation

  • ±24 mA output drive (VCC = 3.0 V)

  • Open-drain outputs

  • Latch-up performance exceeds 250 mA

  • Direct interface with TTL levels

  • Complies with JEDEC standard:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

    • JESD36 (4.5 V to 5.5 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。

型號(hào) 可訂購(gòu)的器件編號(hào),(訂購(gòu)碼(12NC)) 狀態(tài) 標(biāo)示 封裝 外形圖 回流焊/波峰焊 包裝
74LVC2G38GM 74LVC2G38GM,115
(935277241115)
Obsolete no package information
74LVC2G38GM,125
(935277241125)
Obsolete

環(huán)境信息

下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。

型號(hào) 可訂購(gòu)的器件編號(hào) 化學(xué)成分 RoHS RHF指示符
74LVC2G38GM 74LVC2G38GM,115 74LVC2G38GM rohs rhf rhf
74LVC2G38GM 74LVC2G38GM,125 74LVC2G38GM rohs rhf rhf
品質(zhì)及可靠性免責(zé)聲明

文檔 (4)

文件名稱 標(biāo)題 類型 日期
74LVC2G38 Dual 2-input NAND gate; open drain Data sheet 2024-04-30
AN10161 PicoGate Logic footprints Application note 2002-10-29
AN11009 Pin FMEA for LVC family Application note 2019-01-09
lvc2g38 74LVC2G38 IBIS model IBIS model 2014-10-20

支持

如果您需要設(shè)計(jì)/技術(shù)支持,請(qǐng)告知我們并填寫(xiě) 應(yīng)答表 我們會(huì)盡快回復(fù)您。

模型

文件名稱 標(biāo)題 類型 日期
lvc2g38 74LVC2G38 IBIS model IBIS model 2014-10-20

PCB Symbol, Footprint and 3D Model

Model Name 描述

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

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