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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調節(jié)ESD保護

MOSFET

氮化鎵場效應晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應用認證產品(AEC-Q100/Q101)

74LVC3G34DP

Triple buffer

The 74LVC3G34 is a triple buffer. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 1.65 V to 5.5 V

  • Overvoltage tolerant inputs to 5.5 V

  • High noise immunity

  • ±24 mA output drive (VCC = 3.0 V)

  • CMOS low power consumption

  • Latch-up performance exceeds 250 mA

  • Direct interface with TTL levels

  • Complies with JEDEC standard:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

    • JESD36 (4.5 V to 5.5 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

參數類型

型號 VCC (V) Logic switching levels Output drive capability (mA) fmax (MHz) Nr of bits Power dissipation considerations Tamb (°C) Rth(j-a) (K/W) Rth(j-c) (K/W) Package name
74LVC3G34DP 1.65?-?5.5 CMOS/LVTTL ± 32 175 3 low -40~125 217 106 TSSOP8

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

型號 可訂購的器件編號,(訂購碼(12NC)) 狀態(tài) 標示 封裝 外形圖 回流焊/波峰焊 包裝
74LVC3G34DP 74LVC3G34DP,125
(935275566125)
Active V34 SOT505-2
TSSOP8
(SOT505-2)
SOT505-2 SOT505-2_125

環(huán)境信息

型號 可訂購的器件編號 化學成分 RoHS RHF指示符
74LVC3G34DP 74LVC3G34DP,125 74LVC3G34DP rohs rhf rhf
品質及可靠性免責聲明

文檔 (10)

文件名稱 標題 類型 日期
74LVC3G34 Triple buffer Data sheet 2024-08-12
AN10161 PicoGate Logic footprints Application note 2002-10-29
AN11009 Pin FMEA for LVC family Application note 2019-01-09
Nexperia_document_guide_MiniLogic_PicoGate_201901 PicoGate leaded logic portfolio guide Brochure 2019-01-07
SOT505-2 3D model for products with SOT505-2 package Design support 2019-01-18
lvc3g34 74LVC3G34 IBIS model IBIS model 2015-01-15
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT505-2 plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm body Package information 2022-06-03
SOT505-2_125 TSSOP8; Reel pack for SMD, 7''; Q3/T4 product orientation Packing information 2020-04-21
74LVC3G34DP_Nexperia_Product_Reliability 74LVC3G34DP Nexperia Product Reliability Quality document 2025-03-20

支持

如果您需要設計/技術支持,請告知我們并填寫 應答表 我們會盡快回復您。


Longevity

The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.


模型

文件名稱 標題 類型 日期
lvc3g34 74LVC3G34 IBIS model IBIS model 2015-01-15
SOT505-2 3D model for products with SOT505-2 package Design support 2019-01-18

PCB Symbol, Footprint and 3D Model

Model Name 描述

訂購、定價與供貨

型號 Orderable part number Ordering code (12NC) 狀態(tài) 包裝 Packing Quantity 在線購買
74LVC3G34DP 74LVC3G34DP,125 935275566125 Active SOT505-2_125 3,000 訂單產品

樣品

作為 Nexperia 的客戶,您可以通過我們的銷售機構訂購樣品。

如果您沒有 Nexperia 的直接賬戶,我們的全球和地區(qū)分銷商網絡可為您提供 Nexperia 樣品支持。查看官方經銷商列表。

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

可訂購部件

型號 可訂購的器件編號 訂購代碼(12NC) 封裝 從經銷商處購買
74LVC3G34DP 74LVC3G34DP,125 935275566125 SOT505-2 訂單產品
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