可訂購部件
| 型號 | 可訂購的器件編號 | 訂購代碼(12NC) | 封裝 | 從經(jīng)銷商處購買 |
|---|---|---|---|---|
| 74AUP1T00GW | 74AUP1T00GWH | 935690039125 | SOT353-1 | 訂單產(chǎn)品 |
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Click here for more information74AUP1T00GW
Low-power 2-input NAND gate with voltage-level translator
The 74AUP1T00 provides the single 2-input NAND function. This device ensures a very low static and dynamic power consumption across the entire VCC range from 2.3 V to 3.6 V.
The 74AUP1T00 is designed for logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single 2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from 3.6 V to 2.3 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire VCC range.
Features and benefits
Wide supply voltage range from 2.3 V to 3.6 V
High noise immunity
Low static power consumption; ICC = 1.5 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial power-down mode operation
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
參數(shù)類型
| 型號 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | Category |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1T00GW | 2.3?-?3.6 | CMOS | ± 4 | 3.8 | 70 | 1 | ultra low | -40~125 | 316 | 86 | 186 | TSSOP5 | Uni-directional |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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封裝
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74AUP1T00GW | 74AUP1T00GWH (935690039125) |
Active | 5a |
TSSOP5 (SOT353-1) |
SOT353-1 |
WAVE_BG-BD-1
|
SOT353-1_125 |
文檔 (13)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74AUP1T00 | Low-power 2-input NAND gate with voltage-level translator | Data sheet | 2023-07-21 |
| Nexperia_document_guide_Logic_translators | Nexperia Logic Translators | Brochure | 2021-04-12 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT353-1 | 3D model for products with SOT353-1 package | Design support | 2019-09-23 |
| aup1t00 | IBIS model of 74AUP1T00 | IBIS model | 2017-12-14 |
| Nexperia_74AUP1Txx_voltage_translators | Single supply logic gates with voltage translation | Leaflet | 2018-06-18 |
| Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Leaflet | 2019-04-12 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP5_SOT353-1_mk | plastic, thin shrink small outline package; 5 leads; 0.65 mm pitch; 2 mm x 1.25 mm x 0.95 mm body | Marcom graphics | 2018-07-25 |
| SOT353-1 | plastic thin shrink small outline package; 5 leads; body width 1.25 mm | Package information | 2022-11-15 |
| SOT353-1_125 | TSSOP5; Reel pack for SMD, 7"; Q3/T4 product orientation | Packing information | 2023-02-21 |
| 74AUP1T00GW_Nexperia_Product_Reliability | 74AUP1T00GW Nexperia Product Reliability | Quality document | 2024-06-16 |
| WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
訂購、定價與供貨
| 型號 | Orderable part number | Ordering code (12NC) | 狀態(tài) | 包裝 | Packing Quantity | 在線購買 |
|---|---|---|---|---|---|---|
| 74AUP1T00GW | 74AUP1T00GWH | 935690039125 | Active | SOT353-1_125 | 3,000 | 訂單產(chǎn)品 |
樣品
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74AUP1T00GW
Low-power 2-input NAND gate with voltage-level translator
從安世半導體購買
| SKU | 庫存* | MOQ | 單位價格 | 數(shù)量 |
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