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雙極性晶體管

二極管

ESD保護(hù)、TVS、濾波和信號(hào)調(diào)節(jié)ESD保護(hù)

MOSFET

氮化鎵場效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應(yīng)用認(rèn)證產(chǎn)品(AEC-Q100/Q101)

74LVC1G53DP

2-channel analog multiplexer/demultiplexer

The 74LVC1G53 is a single-pole double-throw analog switch with a digital select input (S), two independent inputs/outputs (Y0 and Y1), a common input/output (Z) and a digital enable input (E). When E is HIGH, the switch is turned off. Control inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at control inputs makes the circuit tolerant of slower input rise and fall times.

Features and benefits

  • Wide supply voltage range from 1.65 V to 5.5 V

  • Very low ON resistance:

    • 7.5 Ω (typical) at VCC = 2.7 V

    • 6.5 Ω (typical) at VCC = 3.3 V

    • 6 Ω (typical) at VCC = 5 V

  • Switch current capability of 32 mA

  • High noise immunity

  • CMOS low power consumption

  • TTL interface compatibility at 3.3 V

  • Latch-up performance meets requirements of JESD 78 Class I

  • Control inputs accept voltages up to 5 V

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

參數(shù)類型

型號(hào) Configuration VCC (V) Logic switching levels RON (Ω) RON(FLAT) (Ω) f(-3dB) (MHz) THD (%) Xtalk (dB) Power dissipation considerations Tamb (°C) Package name
74LVC1G53DP SPDT-Z 1.65?-?5.5 CMOS/LVTTL 15 1.5 300 0.078 - very low -40~125 TSSOP8

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

型號(hào) 可訂購的器件編號(hào),(訂購碼(12NC)) 狀態(tài) 標(biāo)示 封裝 外形圖 回流焊/波峰焊 包裝
74LVC1G53DP 74LVC1G53DP,125
(935279944125)
Active V53 SOT505-2
TSSOP8
(SOT505-2)
SOT505-2 SOT505-2_125

環(huán)境信息

型號(hào) 可訂購的器件編號(hào) 化學(xué)成分 RoHS RHF指示符
74LVC1G53DP 74LVC1G53DP,125 74LVC1G53DP rohs rhf rhf
品質(zhì)及可靠性免責(zé)聲明

文檔 (10)

文件名稱 標(biāo)題 類型 日期
74LVC1G53 2-channel analog multiplexer/demultiplexer Data sheet 2024-04-30
AN10161 PicoGate Logic footprints Application note 2002-10-29
AN11009 Pin FMEA for LVC family Application note 2019-01-09
Nexperia_document_guide_MiniLogic_PicoGate_201901 PicoGate leaded logic portfolio guide Brochure 2019-01-07
SOT505-2 3D model for products with SOT505-2 package Design support 2019-01-18
lvc1g53 74LVC1G53 IBIS model IBIS model 2015-02-19
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT505-2 plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm body Package information 2022-06-03
SOT505-2_125 TSSOP8; Reel pack for SMD, 7''; Q3/T4 product orientation Packing information 2020-04-21
74LVC1G53DP_Nexperia_Product_Reliability 74LVC1G53DP Nexperia Product Reliability Quality document 2024-06-16

支持

如果您需要設(shè)計(jì)/技術(shù)支持,請告知我們并填寫 應(yīng)答表 我們會(huì)盡快回復(fù)您。

模型

文件名稱 標(biāo)題 類型 日期
lvc1g53 74LVC1G53 IBIS model IBIS model 2015-02-19
SOT505-2 3D model for products with SOT505-2 package Design support 2019-01-18

PCB Symbol, Footprint and 3D Model

Model Name 描述

訂購、定價(jià)與供貨

型號(hào) Orderable part number Ordering code (12NC) 狀態(tài) 包裝 Packing Quantity 在線購買
74LVC1G53DP 74LVC1G53DP,125 935279944125 Active SOT505-2_125 3,000 訂單產(chǎn)品

樣品

作為 Nexperia 的客戶,您可以通過我們的銷售機(jī)構(gòu)訂購樣品。

如果您沒有 Nexperia 的直接賬戶,我們的全球和地區(qū)分銷商網(wǎng)絡(luò)可為您提供 Nexperia 樣品支持。查看官方經(jīng)銷商列表

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

可訂購部件

型號(hào) 可訂購的器件編號(hào) 訂購代碼(12NC) 封裝 從經(jīng)銷商處購買
74LVC1G53DP 74LVC1G53DP,125 935279944125 SOT505-2 訂單產(chǎn)品
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