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雙極性晶體管

二極管

ESD保護(hù)、TVS、濾波和信號調(diào)節(jié)ESD保護(hù)

MOSFET

氮化鎵場效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應(yīng)用認(rèn)證產(chǎn)品(AEC-Q100/Q101)

74ALVCH32973EC

16-bit bus transceiver and transparant D-type latch with 8 independent buffers

The 74ALVCH32973 is a 16-bit bus transceiver and transparent D-type latch with 8 independent buffers with bus hold inputs and 3-state outputs. It features direction (1DIR, 2DIR), latch enable (1LOE, 2LOE), transceiver output enable (1TOE, 2TOE) and latch enable (1LE, 2LE) control inputs; four 8-bit transceiver ports (1An, 2An & 1Bn, 2Bn); two 8-bit D-type latch output ports (1Qn, 2Qn) and an 8-bit buffer with data inputs Dn and outputs Yn. The configuration of the control pins allows the device to be used as one 8-bit buffer, two 8-bit transceivers, and two 8-bit latches or one 8-bit buffer, one 16-bit transceiver and one 16-bit latch.

The 8-bit buffer functions independently of the control inputs. The direction of data transmission between A and B is controlled by nDIR and when nTOE is set HIGH the A and B ports will assume a HIGH-impedance OFF-state, they will be effectively isolated. When nLE is HIGH, data at the A inputs enter the latches. In this condition the latches are transparent, a Q output will change each time its corresponding A-input changes. When nLE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nLOE causes the Q outputs to assume a high-impedance OFF-state. Operation of the nLOE input does not affect the state of the latches.

此產(chǎn)品已停產(chǎn)

Features and benefits

  • Wide supply voltage range from 1.2 V to 3.6 V
  • Complies with JEDEC standard JESD8-B
  • CMOS low power consumption
  • Direct interface with TTL levels
  • All data inputs have bus hold
  • Output drive capability 50 Ω transmission lines at 85 °C
  • Current drive ±24 mA at VCC = 3.0 V

Applications

    參數(shù)類型

    型號 Package name
    74ALVCH32973EC LFBGA96

    Series

    文檔 (1)

    文件名稱 標(biāo)題 類型 日期
    74ALVCH32973 16-bit bus transceiver and transparant D-type latch with 8 independent buffers Data sheet 2017-05-03

    支持

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    Longevity

    The Nexperia Longevity Program is aimed to provide our customers information from time to time about the expected time that our products can be ordered. The NLP is reviewed and updated regularly by our Executive Management Team. View our longevity program here.


    模型

    No documents available

    How does it work?

    The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

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