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雙極性晶體管

二極管

ESD保護(hù)、TVS、濾波和信號(hào)調(diào)節(jié)ESD保護(hù)

MOSFET

氮化鎵場(chǎng)效應(yīng)晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應(yīng)用認(rèn)證產(chǎn)品(AEC-Q100/Q101)

74LVT573DB

3.3 V octal D-type transparent latch; 3-state

The 74LVT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs

此產(chǎn)品已停產(chǎn)

Features and benefits

  • Wide supply voltage range from 2.7 to 3.6 V

  • Inputs and outputs arranged for easy interfacing to microprocessors

  • 3-state outputs for bus interfacing

  • Common output enable control

  • Overvoltage tolerant inputs to 5.5 V

  • BiCMOS high speed and output drive

  • Direct interface with TTL levels

  • Input and output interface capability to systems at 5 V supply

  • Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs

  • Live insertion and extraction permitted

  • No bus current loading when output is tied to 5 V bus

  • Power-up reset

  • Power-up 3-state

  • IOFF circuitry provides partial Power-down mode operation

  • Latch-up performance exceeds 500 mA per JESD 78 Class II Level B

  • Complies with JEDEC standard JESD8C (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C

參數(shù)類型

型號(hào) Package name
74LVT573DB SSOP20

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。

型號(hào) 可訂購(gòu)的器件編號(hào),(訂購(gòu)碼(12NC)) 狀態(tài) 標(biāo)示 封裝 外形圖 回流焊/波峰焊 包裝
74LVT573DB 74LVT573DB,118
(935170710118)
Withdrawn / End-of-life SOT339-1
SSOP20
(SOT339-1)
SOT339-1 SSOP-TSSOP-VSO-WAVE
SOT339-1_118
74LVT573DB,112
(935170710112)
Obsolete 暫無(wú)信息

環(huán)境信息

下表中的所有產(chǎn)品型號(hào)均已停產(chǎn) 。

型號(hào) 可訂購(gòu)的器件編號(hào) 化學(xué)成分 RoHS RHF指示符
74LVT573DB 74LVT573DB,118 74LVT573DB rohs rhf rhf
74LVT573DB 74LVT573DB,112 74LVT573DB rohs rhf rhf
品質(zhì)及可靠性免責(zé)聲明

文檔 (6)

文件名稱 標(biāo)題 類型 日期
74LVT573 3.3 V octal D-type transparent latch; 3-state Data sheet 2024-06-07
lvt573 lvt573 IBIS model IBIS model 2013-04-09
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT339-1 plastic, shrink small outline package; 20 leads; 0.65 mm pitch; 7.2 mm x 5.3 mm x 2 mm body Package information 2020-04-21
lvt lvt Spice model SPICE model 2013-05-07
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

如果您需要設(shè)計(jì)/技術(shù)支持,請(qǐng)告知我們并填寫(xiě) 應(yīng)答表 我們會(huì)盡快回復(fù)您。

模型

文件名稱 標(biāo)題 類型 日期
lvt573 lvt573 IBIS model IBIS model 2013-04-09
lvt lvt Spice model SPICE model 2013-05-07

PCB Symbol, Footprint and 3D Model

Model Name 描述

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

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