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Click here for more information74LVC2G00GF
Dual 2-input NAND gate
The 74LVC2G00 is a dual 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Alternatives
Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
±24 mA output drive (VCC = 3.0 V)
CMOS low power dissipation
IOFF circuitry provides partial Power-down mode operation
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Overvoltage tolerant inputs to 5.5 V
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
參數(shù)類型
| 型號 | Package name |
|---|---|
| 74LVC2G00GF | XSON8 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
|
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封裝
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號，（訂購碼(12NC)） | 狀態(tài) | 標示 | 封裝 | 外形圖 | 回流焊/波峰焊 | 包裝 |
|---|---|---|---|---|---|---|---|
| 74LVC2G00GF | 74LVC2G00GF,115 (935291501115) |
Withdrawn / End-of-life |
XSON8 (SOT1089) |
SOT1089 |
REFLOW_BG-BD-1
|
SOT1089_115 |
環(huán)境信息
下表中的所有產(chǎn)品型號均已停產(chǎn) 。
| 型號 | 可訂購的器件編號 | 化學成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC2G00GF | 74LVC2G00GF,115 | 74LVC2G00GF |
|
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Series
文檔 (10)
| 文件名稱 | 標題 | 類型 | 日期 |
|---|---|---|---|
| 74LVC2G00 | Dual 2-input NAND gate | Data sheet | 2024-05-08 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| Nexperia_document_guide_MiniLogic_MicroPak_201808 | MicroPak leadless logic portfolio guide | Brochure | 2018-09-03 |
| SOT1089 | 3D model for products with SOT1089 package | Design support | 2019-10-07 |
| lvc2g00 | 74LVC2G00 IBIS model | IBIS model | 2014-10-20 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| XSON8_SOT1089_mk | plastic, extremely thin small outline package; no leads; 8 terminals; 0.55 mm pitch; 1.35 mm x 1 mm x 0.5 mm body | Marcom graphics | 2017-01-28 |
| SOT1089 | plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.5 mm body | Package information | 2022-06-03 |
| REFLOW_BG-BD-1 | Reflow soldering profile | Reflow soldering | 2021-04-06 |
| MAR_SOT1089 | MAR_SOT1089 Topmark | Top marking | 2013-06-03 |
How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74LVC2G00GF
Dual 2-input NAND gate
從安世半導體購買
| SKU | 庫存* | MOQ | 單位價格 | 數(shù)量 |
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