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雙極性晶體管

二極管

ESD保護、TVS、濾波和信號調節(jié)ESD保護

MOSFET

氮化鎵場效應晶體管(GaN FET)

絕緣柵雙極晶體管(IGBTs)

模擬和邏輯IC

汽車應用認證產品(AEC-Q100/Q101)

74LVC132APW

Quad 2-input NAND Schmitt trigger

The 74LVC132A provides four 2-input NAND gates with Schmitt trigger inputs. It is capable of transforming slowly-changing input signals into sharply defined, jitter-free output signals.

The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environment.

Features and benefits

  • Wide supply voltage range from 1.2 V to 3.6 V

  • 5 V tolerant inputs for interfacing with 5 V logic

  • CMOS low-power consumption

  • Direct interface with TTL levels

  • Unlimited input rise and fall times

  • Inputs accept voltages up to 5.5 V

  • Complies with JEDEC standard JESD8-C/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Applications

  • Wave and pulse shapers for highly noisy environments

  • Astable multivibrator

  • Monostable multivibrator.

參數類型

型號 VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) fmax (MHz) Nr of bits Power dissipation considerations Tamb (°C) Rth(j-a) (K/W) Ψth(j-top) (K/W) Rth(j-c) (K/W) Package name
74LVC132APW 1.2?-?3.6 CMOS/LVTTL ± 24 3.4 175 4 low -40~125 143 8.4 69 TSSOP14

PCB Symbol, Footprint and 3D Model

Model Name 描述

封裝

型號 可訂購的器件編號,(訂購碼(12NC)) 狀態(tài) 標示 封裝 外形圖 回流焊/波峰焊 包裝
74LVC132APW 74LVC132APW,118
(935282823118)
Active LVC132A SOT402-1
TSSOP14
(SOT402-1)
SOT402-1 SSOP-TSSOP-VSO-WAVE
SOT402-1_118

環(huán)境信息

型號 可訂購的器件編號 化學成分 RoHS RHF指示符
74LVC132APW 74LVC132APW,118 74LVC132APW rohs rhf rhf
品質及可靠性免責聲明

文檔 (11)

文件名稱 標題 類型 日期
74LVC132A Quad 2-input NAND Schmitt trigger Data sheet 2024-02-12
AN11009 Pin FMEA for LVC family Application note 2019-01-09
AN263 Power considerations when using CMOS and BiCMOS logic devices Application note 2023-02-07
SOT402-1 3D model for products with SOT402-1 package Design support 2023-02-02
lvc132a lvc132a IBIS model IBIS model 2018-11-28
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
TSSOP14_SOT402-1_mk plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body Marcom graphics 2017-01-28
SOT402-1 plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.2 mm body Package information 2023-11-07
SOT402-1_118 TSSOP14; Reel pack for SMD, 13"; Q1/T1 product orientation Packing information 2025-01-14
74LVC132APW_Nexperia_Product_Reliability 74LVC132APW Nexperia Product Reliability Quality document 2024-06-16
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

如果您需要設計/技術支持,請告知我們并填寫 應答表 我們會盡快回復您。

模型

文件名稱 標題 類型 日期
lvc132a lvc132a IBIS model IBIS model 2018-11-28
SOT402-1 3D model for products with SOT402-1 package Design support 2023-02-02

PCB Symbol, Footprint and 3D Model

Model Name 描述

訂購、定價與供貨

型號 Orderable part number Ordering code (12NC) 狀態(tài) 包裝 Packing Quantity 在線購買
74LVC132APW 74LVC132APW,118 935282823118 Active SOT402-1_118 2,500 訂單產品

樣品

作為 Nexperia 的客戶,您可以通過我們的銷售機構訂購樣品。

如果您沒有 Nexperia 的直接賬戶,我們的全球和地區(qū)分銷商網絡可為您提供 Nexperia 樣品支持。查看官方經銷商列表

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

可訂購部件

型號 可訂購的器件編號 訂購代碼(12NC) 封裝 從經銷商處購買
74LVC132APW 74LVC132APW,118 935282823118 SOT402-1 訂單產品
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